1. Technical Field
The embodiments described herein relate to a test circuit and, more particularly, to a wafer burn-in test circuit capable of using a dynamic stress.
2. Related Art
Generally, a burn-in test process, which screens a device failure at an early stage, is carried out after manufacturing a semiconductor memory device. A conventional burn-in test is performed to improve the reliability of the semiconductor memory device.
In more detail, the burn-in test is often used as a screen test to sort a bad device at an early stage. The burn-in test can be classified into a wafer burn-in test carried out in a wafer state and a package burn-in test carried out in a package state.
The wafer burn-in test is carried out by applying stress to word lines over a predetermined time under the condition of high temperature and high voltage, after activating the word lines in memory cells. That is, this is a test to verify a latency defectiveness, which can be caused at an early stage when a stress is applied to memory cells. However, this wafer burn-in test has a problem in that it is difficult to screen the defectiveness effectively at an early stage. Namely, similar to the package burn-in test, it is also required to apply a dynamic stress to a memory cell in the worst condition in a wafer bur-in test mode.